The Carbon Nanotubes (CNT) are viewed to be a new key element for future electronics and photonics. In the semiconductor type CNT, such unique properties as quantization of the electron spectrum, ballistic electron propagation along the tube, current densities as high as 109 A/cm2, existence of the semiconductor phase, possibilities for n- and p-doping with a high carrier mobility, as well as excellent thermal conductance, make the nanotubes a great candidate for future high-speed, high efficiency electronic and photonic devices.
The key element currently used in the electronic circuits is the Si-based transistor. It is important for future nanotube applications to reproduce such an element using CNT technology. Such attempts have been carried out in many research institutions worldwide. The proof-of-concept design, used in all works, where a single nanotube is placed horizontally on the substrate between the contacts, is utilized in essentially all publication on this topic (see e.g. E. Ungersboeck, et al, IEEE Transactions on nanotechnology, V4, p. 533, 2005). The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing. The future success of CNT devices will rely on emergence of a cost efficient manufacturing process that will ensure a high-yield and cost efficiency above the modern transistor technology.
The present invention relates to this technology. It is based on the growth of a nanotube or controllable nanotube array on a metal electrode normally to the electrode plane and then sequential deposition of dielectric and metal layers to produce a solid platform for attachment of a second common contact to all the nanotube tips, thereby forming source and drain electrodes. The transistor gate electrode is made as a third conductive layer sandwiched between the dielectric layers and placed somewhere in the middle of the nanotube length. The CNT transistor structure can be made on a simple glass substrate or any other substrates, including a Si wafer.
Such a technology was presented in the U.S. Pat. No. 7,851,784 by A. Kastalsky, where several semiconductor nanotube array devices and method for their fabrication have been disclosed. Shown in FIG. 1 as a Prior Art, is the nanotube array FET in which the nanotubes are grown normally to the substrate, and the gate electrode 51 is attached to the sidewall of every nanotube 57 in the array through a layer of insulator 54. The key element is the metal layer 51 in the middle of the nanotube length, sandwiched between two insulator layers 52 and 53. During deposition of the first insulator layer 52, a thin layer of insulation material will also be deposited on the nanotube walls, thereby forming a gate insulator layer 54 around each nanotube. It is then followed by deposition of the gate metal layer 51 and the insulator layer 53. After polishing of the insulator layer 53 and exposure of the nanotube tips, the top metal layer 55 (the drain electrode) is deposited to complete the structure. Such a design of the CNT transistor, with the nanotube buried within sequentially deposited insulating and metal layers, allows realization of the planar technology for commercial manufacturing of the CNT-based transistors and circuits.
The described above transistor design is MOSFET-like, i.e. it relies on the gate insulator layer 54 placed between the gate metal layer 51 and the nanotube. To provide a good IC performance, the gate insulator must be rather thin, pin-hole free and spatially uniform within each nanotube and over the entire CNT array. In Si-based ICs, the quality of this layer (typically ˜5 nm-thick layer of SiO2 grown at high temperatures by silicon surface oxidation) represents the key element of the device processing. All presented in the literature CNT transistors employ such a MOSFET concept.
The CNT transistors, according to the present invention, rely on different device operational principles and fabrication process. Unlike the MOSFET, they do not contain the gate insulator layer. All three devices disclosed have three Schottky barriers attached to the vertically grown nanotube. Two of them of the same Schottky barrier height are attached to the nanotube ends, thereby forming the contacts to the nanotube, while the third one having different barrier height than previous two is attached directly to the nanotube somewhere in the middle of the nanotube length.
The first CNT device, according to the present invention, represents a MESFET-like transistor (see. e.g. S. Sze, Physics of semiconductor devices, Wiley & Sons, 1969, p. 410), wherein a high Schottky barrier at the middle of the nanotube forms the gate electrode by direct contact to the nanotube, while two contact pads having a low Schottky barrier at the nanotube ends form ohmic contacts and represent source and drain electrodes to the nanotube channel. The MESFET is known to have a high speed of operation and is used in high-frequency amplifiers. As discussed below, the advantages of the nanotube properties and device design introduce additional high-speed benefits. This device is the first object of the present invention.
The second CNT transistor of the present invention relies on a carrier tunneling through the Schottky barrier and ballistic carrier transport along the nanotube, In this case, relatively high energy Schottky barriers are attached to the nanotube ends and free carriers (in the presented design holes) tunnel into the nanotube through the Schottky barrier at the emitter side of the nanotube. If the nanotube length is made shorter than the ballistic mean-free path, the carriers move without losing energy along the entire nanotube directly into the appropriately biased collector electrode and over the collector Schottky barrier. The Schottky barrier at the middle of the nanotube is low and forms an ohmic contact to the base.
The success of operation of this ballistic CNT transistor depends on the ratio of the nanotube length and ballsistic mean-free path, see below. The semiconductor analogue of such a ballistic transistor, belongs to a class of Hot Electron Transistors (HET), see e.g. M. Heiblum et al. Phys. Rev. Lett. 55, 2200 (1985), and relies on the carrier ballistic travelling across the GaAs base in the GaAs/AlGaAs heterostructure. In these publications, some ballistic transport was registered only at low temperatures because of low energy heterostructure barriers. In addition, a tradeoff between the base thickness (which is needed to be very thin, ˜10 nm) and the base lateral series resistance (which increases as the base becomes thinner) renders unrealistic the realization of the semiconductor version of this device.
On the other hand, in the SWCNT the room temperature ballistic mean-free path can be as long as 700 nm, see M. Fuhrer et al. Electronic Properties of Molecular Nanostructures, edited by H. Kuzmany, 2001. Therefore, ˜600 nm-long nanotube will be sufficient for HET operations. This device is the second object of the present invention. The third device, according to the present invention, has similar device structure and the same Schottky barriers heights as in the above discussed CNT HET. When both Schottky barriers at the nanotube ends are equally biased relatively to the ohmic contact at the middle of the nanotube, carriers tunnel from both nanotube ends into the nanotube body and then, moving ballistically, relax between the quantum levels. There is a probability that the energy loss occurs in this case partially through the process of intra-subband photon emission. Thus, in such an arrangement the device can be used as a Photon Emitter.
The two-electrode intra-band photon emitter has been disclosed by A. Kastalsky in the U.S. Pat. No. 7,728,333, wherein the carrier tunneling into the nanotube occurs only from one contact at the nanotube end. It is followed by movement of the injected carriers ballistically to the opposite, ohmic, contact in the nanotube. Three-terminal design, disclosed in the present invention, with carrier injection from both ends of the nanotube, and therefore with carrier traveling to the ohmic contact within only half of the nanotube length, simplifies the fulfillment of necessary condition of carrier ballistic propagation along the nanotube and thus improves the photon emission efficiency. The intra-band, three-terminal CNT Photon Emitter (CNT PE) represents the third object of the present invention.